Low compliance tester interface

ABSTRACT

Automatic test equipment adapted for testing a plurality of devices-under-test (DUTs) is disclosed. The automatic test equipment includes a mainframe computer and a test head coupled to the mainframe computer. The test head includes a low-profile tester interface having a first interface board and a device board. The device board engages contact points on the DUTs and includes a topside. A hard stop is mounted to the first interface board and defines a reference plane. The hard stop is adapted to engage the device board topside to vertically fix the device board positionally with respect to the first interface board. The automatic test equipment further includes a compliant interconnect array adapted for compression between the first interface board and the device board. The array includes a plurality of elastomeric connectors, each comprising a thin layer of foam material and a plurality of formed contact pins. The pins are embedded in spaced-apart relationship in the foam material. Each of the contact pins includes a substantially straight body of a first thickness and having respective ends bounded by integrally formed and oppositely projecting horizontal tabs. The tabs have respective contact engagement surfaces and are formed with a dimple disposed on the contact engagement surface to provide greater contact engagement reliability.

[0001] This is a Continuation-In-Part of U.S. patent application Ser.No. 09/571,563, filed May 15, 2000, now pending.

FIELD OF THE INVENTION

[0002] The invention relates generally to automatic test equipment andmore particularly a low compliance tester interface for reliablycoupling a semiconductor tester to one or more semiconductordevices-under-test.

BACKGROUND OF THE INVENTION

[0003] In the automatic test equipment industry, one of the fundamentalchallenges to testing a plurality of semiconductor devices in parallelinvolves routing and connecting thousands of ground, signal and powerpaths (collectively defining tester channels) from the tester channelcards to the device(s)-under-test (DUTs). As shown generally in FIG. 1,a semiconductor tester 10 usually includes a mainframe computer 12 thatinteracts with a test head 14. The test head houses the tester channelcards that generate and receive test signals for application to andreceipt from the individual DUT contacts formed on a semiconductor wafer16. In order to facilitate the eventual connection between each DUT pinand a tester channel, the signal paths from the test head to the DUT arerouted through a tester interface 18. The interface directs the pathsfrom the low-density test head area to the very high dense probe arraydisposed proximate the DUTs.

[0004] Referring now to FIG. 2, one conventional tester interface forapplication to wafer-level testing, generally designated 20, includes aprober interface board (PIB) 22 comprising a multi-layer circuit board.The PIB includes upper surface contacts (not shown) for coupling torespective channel card coaxial cables (not shown). Lower surfacecontacts disposed on the PIB underside are arranged in a high-densityannular array, and connected to the upper contacts by respectiveinternal electrical paths.

[0005] Further referring to FIG. 2, the underside PIB contactscorrespond to a matching array of connection points on a probecard 24.Like the PIB, the probecard comprises a multi-layer circuit board thatgenerally routes the signal, ground and power paths from its outerperiphery to a centrally disposed probe array 26. A compliantinterconnect array 28 electrically couples the PIB and probecardtogether. The probe array, during test, touches down onto thesemiconductor wafer (not shown) to effect the tester connection to oneor more semiconductor devices formed thereon.

[0006] Conventional probecards are typically formed in a laminatedstructure that includes, for example, thirty or more layers, andmeasures around 0.250 inch thick. Because of the manufacturingcomplexities associated with such structures, tolerance deviations inthe probecard thickness on the order of around +/−0.025 inch are common.Since the surface area of a typical probecard is on the order ofapproximately 120 square inches, planarity and thickness variations posea significant challenge to interface designs that require thousands ofboard-to-board connections over much of the surface area. Moreover, asshown in FIG. 2, during operation the probecard tends to deflect nearthe center portion because of the large number of electrical connectionsbetween the wafer and probe array that, taken as a whole, exert asubstantial force on the order of around a hundred pounds. Usually, astiffener 29 is mounted to the probecard in an effort to reduce thedeflection. Unfortunately, many areas where electrical contacts touchcannot be backed-up by a stiffener.

[0007] The planarity and deflection variations of the PIB and probecardtypically have an effect on the assembled tolerance of the vertical, or“Z”-dimension, stack height. Conventionally, the stack height is definedwith respect to the bottom of the probecard, thereby including theuncertainty of the probecard thickness in the overall height. Keepingthe overall stack height within specified tolerances is very importantto ensure acceptable tester performance.

[0008] In an effort to compensate for the variations in probecard andPIB thickness and planarities introduced by manufacturing processes andoperation induced deflection, and to ensure a constant connectionbetween the PIB and the probecard, ATE manufacturers have typicallyimplemented a tester interface that employs a conventional pogopin-based interconnect array. As is well known in the art, conventionalpogo pins are barrel-shaped contacts having spring-loaded tips thatprovide a relatively large mechanical compliance up to around 0.125inch. Having the large compliance allows the assembly of the interfacestack to include the PIB and probecard tolerance deviations.

[0009] Although pogo pins generally provide a relatively long compliancelength, the overall cost and reliability of conventional pogo pins arebelieved undersirable for the next-generation of semiconductor testers.This belief stems from findings that pogo pin tips are often prone tobreakage, possibly substantially affecting a tester's reliability factorin terms of mean-time-between-failure (MTBF). Moreover, the relativelylong travel capability, or compliance, for conventional pogo pinsundesirably affects the impedance controlled transmission linecharacteristic for individual signals. As semiconductor device speedsincrease beyond 250 MHz, transmission line quality becomes much moreimportant.

[0010] What is needed and heretofore unavailable is a low compliance,low cost tester interface having the capability of reliably makingtester board-to-board connections. Moreover, the need exists for such aninterface that requires little to no modifications to user-controlledhardware. The tester interface of the present invention satisfies theseneeds.

SUMMARY OF THE INVENTION

[0011] The tester interface of the present invention provides a lowcompliance and low-cost alternative to conventional high-compliance pogopin schemes while dramatically increasing the reliability ofconnections. This allows for testing of more devices in parallel,contributing to lower test costs per device.

[0012] To realize the foregoing advantages, the invention in one formcomprises automatic test equipment adapted for testing a plurality ofdevices-under-test (DUTs). The automatic test equipment includes amainframe computer and a test head coupled to the mainframe computer.The test head includes a low-profile tester interface having a firstinterface board and a device board. The device board engages contactpoints on the DUTs and includes a topside. A hard stop is mounted to thefirst interface board and defines a reference plane. The hard stop isadapted to engage the device board topside to vertically fix the deviceboard positionally with respect to the first interface board. Theautomatic test equipment further includes a compliant interconnect arrayadapted for compression between the first interface board and the deviceboard. The array includes a plurality of elastomeric connectors, eachcomprising a thin layer of foam material and a plurality of formedcontact pins. The pins are embedded in spaced-apart relationship in thefoam material. Each of the contact pins includes a substantiallystraight body of a first thickness and having respective ends bounded byintegrally formed and oppositely projecting horizontal tabs. The tabshave respective contact engagement surfaces and are formed with a dimpledisposed on the contact engagement surface to provide greater contactengagement reliability.

[0013] Other features and advantages of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The invention will be better understood by reference to thefollowing more detailed description and accompanying drawings in which

[0015]FIG. 1 is a block diagram of a semiconductor tester;

[0016]FIG. 2 is a cross-sectional view of a conventional wafer-leveltester interface;

[0017]FIG. 3 is a cross-sectional view of a tester interface accordingto one form of the present invention;

[0018]FIG. 4 is a perspective view of the compliant interconnect ring ofFIG. 3;

[0019]FIG. 4a is a cross-sectional view along line 4 a-4 a of FIG. 4;

[0020]FIG. 4b is a perspective view of a contact pin shown in FIG. 4a;and

[0021]FIG. 5 is an enlarged cross-sectional view of area 5-5 of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

[0022] Referring now to FIG. 3, a tester interface for use with asemiconductor parallel tester, generally designated 30, implements ahard stop 70 that abuts the central portion of a device board 50 tominimize the board's operational deflection while simultaneouslydefining a z-stack reference plane. The reference plane fixes the deviceboard vertical position with respect to a first interface board 32.Establishing a top-side reference plane that sets the vertical positionof the device board in this manner enables the use of a low-profileinterconnect array 60 that employs a plurality of disposable,inexpensive and tight-pitch elastomeric connectors 66 (FIG. 4).

[0023] Referring to FIGS. 3 and 4, for wafer probing applications, thefirst interface board 32 comprises a prober interface board (PIB). ThePIB couples to the device board 50 via the compliant interconnect array60 (FIG. 4) and is formed with a central opening 34 and a first planarsurface 36 that mounts a relatively low-density contact array (notshown) for coupling to respective signal, ground and power leads (notshown). A second planar surface 38 disposed opposite the first surfacemounts a relatively high-density array of contact pads (not shown).Internal electrical paths and conductive vias formed on multiple layersof the board connect the first surface contacts to the second surfacecontact array.

[0024] To inhibit deflection of the PIB 32 during operation, a stiffener40 mounts to the PIB and is constructed to roughly match the dimensionsthereof. The stiffener is preferably formed of aluminum and includes acentrally disposed opening aligned concentrically with the PIB opening34.

[0025] Referring again to FIGS. 3 and 5, the device board 50 forwafer-probe applications comprises a probecard adapted for interfacingwith the high-pitch array of contacts disposed on the PIB 32. Theprobecard generally includes a top surface 52 that mounts a peripheralarray of contacts (not shown) that match and align with the array ofcontact pads disposed on the PIB. Conductive paths are formed in theprobecard that couple the array to a fine-pitch contact matrix disposedin the central portion of the probecard known as a probe array 54. Theprobe array employs precision probes 55 for repetitively touching-downon predefined areas of a semiconductor wafer (not shown), enabling thetesting of multiple devices in parallel.

[0026] Like the PIB 32, the probecard 50 is paired with a stiffener 56mounted to the probecard underside for inhibiting deflection duringoperation. For some applications, however, an underside stiffener maynot be necessary for the probe card.

[0027] Referring now to FIGS. 3, 4 and 5, the compliant interconnectarray 60 is adapted for axial alignment between the PIB 32 and theprobecard 50. With specific reference to FIG. 4, the array includes aring-shaped and segmented retainer 62 formed with a plurality of windows64 detachably mounting respective elastomeric connectors 66. Theconnectors preferably take the form of those manufactured under thetrademark ISOCON, by Circuit Components Inc., Tempe, Ariz. Eachconnector forms a “petal” in a corresponding window, and is securedthereto by a suitable silicone adhesive or sealant. The connectors,while relatively thin at around 0.075 to 0.85 inch, provide a maximumcompliance on the order of approximately 0.030 to 0.038 inch.

[0028] With reference to FIGS. 4a and 4 b, one embodiment of theelastomeric connectors 66 includes a plurality of formed contact pins 67embedded in a thin layer of foam-like material 69. Each contact pin 67,shown in further detail in FIG. 4b, is formed with a substantiallystraight rectangular body 71 of a first thickness and bounded at eachend by integrally formed and oppositely projecting horizontal tabs 73.This basic construction is more fully described in U.S. Pat. No.4,793,814 to Zifcak, hereby incorporated by reference in its entirety.As a refinement, however, the tabs are coined to provide sufficientexcess material to form a raised contact dimple 75 on the contactengagement surface 77. Additionally, the edges of the tabs are chamferedat 79 to minimize unwanted electrical contact due to an uneven surface.By constructing the connector contacts in this manner, more reliableconnections between the PIB 32 and the probecard 50 are realized.

[0029] To establish a high tolerance reference plane for verticallypositioning the probecard with respect to the PIB, enabling the use ofthe low-compliance elastomeric connectors 66, a hard stop, generallydesignated 70, is employed on the top-side surface of the probecard. Thehard stop includes a top-side stiffener 72 preferably mounted to theprobecard and having a body that projects vertically from the probecardsurface a predetermined height H, and terminating in a top surface thatdefines a reference plane at 71. The hard stop also includes a rigidflat plate 78 that overlies the top-side stiffener 72 and anchors to thePIB stiffener 40.

[0030] Prior to operation, the PIB 32, probecard 50, and interconnectarray 60 are aligned by the use of alignment pins 80 (FIG. 5) to enablethe “making and breaking” of the densely packed individual electricalconnections. Moreover, the stack height of the interface, known as theZ-stack height, is pre-set through the use of a fixture (not shown) toproperly set an interconnect array gap G (FIG. 5). The gap defines theheight of the interconnect array, which preferably exhibits a lowprofile, for example, of no higher than around 0.076 to 0.085 inch. Thefixture simulates the installation of the probecard, which is usuallycarried out at the semiconductor manufacturing facility. Because thehard stop stiffener height can be more accurately controlled than theprobecard thickness, the compliance tolerance can be reduced.

[0031] In operation, the tester interface 30 is employed in asemiconductor memory tester capable of testing, for example, one-hundredand twenty-eight (or more) semiconductor memory devices in parallel.Such a high number of devices requires upwards of approximately 12,000to 15,000 signal, ground and power connections leading from the testertest head to the probe array. Providing a high level of parallelismmaximizes the level of throughput for the semiconductor manufacturer,thereby reducing unit test costs.

[0032] During test, the tester interface experiences cyclic loading dueto the periodic touch-down of the probe array with respect to the waferunder test. Under typical conditions, the load at the probe array isapproximately sixty to one-hundred pounds. However, due to theimplementation of the top-side stiffener 70 and the hard-stop 78, axialdeflection of the probecard is substantially minimized. Even moreimportantly, since the vertical position of the probecard is fixed withrespect to the hard stop reference plane, the uncertainty in probecardthickness has no effect on the compliance requirement. This directlylowers the required compliance of the interconnect ring 60, enabling theuse of the relatively inexpensive and tight-pitch connection scheme suchas that available with elastomeric connectors.

[0033] Over the course of continuous operation spanning, for example,thousands of hours, maintenance conditions may arise that require thereplacement of one or more connectors within the interconnect ring.Because of the minimal cost of the elastomeric material, and therelative ease of replacement of any individual connector set,replacement costs are substantially mitigated.

[0034] Those skilled in the art will appreciate the many benefits andadvantages afforded by the present invention. Of particular importanceis the ability to use inexpensive, and high-pitch elastomeric connectorsfor interfacing the PIB to the probecard. This not only enables paralleltesting of potentially hundreds of semiconductor devices in parallel,but does so without the need for conventional high-compliance pogo pins.By eliminating expensive high-compliance elements from the interfaceequation, tester reliability time is maximized, greatly contributing toreduced test costs.

[0035] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetail may be made therein without departing from the spirit and scopeof the invention. For example, while the present invention has beendescribed in detail for use in wafer-probe applications, minormodifications could be made to employ the interface in packaged-devicelevel applications. In such circumstances, the first interface boardwould comprise a handler interface board (HIB), while the device boardwould comprise a device interface board (DIB). Moreover, rather thancoupling the tester to a prober, the interface would be coupling thetester to a handler.

[0036] Additionally, the description of the hard stop included hereinspecifically discloses a multi-part structure, while it could alsocomprise an integral unit having, for example, a flange to couple to thefirst interface board and a body projecting vertically from the flange apredetermined height.

What is claimed is:
 1. Automatic test equipment adapted for testing a plurality of device-sunder-test (DUTs), said automatic test equipment including: a mainframe computer; and a test head coupled to said mainframe computer, said test head including a low-profile tester interface, said low-profile tester interface including a first interface board, a device board for engaging contact points on the DUTs, and having a topside, a hard stop mounted to said first interface board and defining a reference plane, said hard stop adapted to engage said device board topside to vertically fix said device board positionally with respect to said first interface board; and a compliant interconnect array adapted for compression between said first interface board and said device board, said array including a plurality of elastomeric connectors, each of said connectors comprising a thin layer of foam material, and a plurality of formed contact pins embedded in spaced-apart relationship in said foam material, each of said contact pins including a substantially straight body of a first thickness and having respective ends bounded by integrally formed and oppositely projecting horizontal tabs, said tabs having respective contact engagement surfaces and formed with a dimple disposed on said contact engagement surface.
 2. Automatic test equipment according to claim 1 wherein: said engagement surfaces are formed with chamfered edges.
 3. An elastomeric connector for use in an ATE interface, said elastomeric connector comprising: a thin layer of foam material; and a plurality of formed contact pins embedded in spaced-apart relationship in said foam material, each of said contact pins including a substantially straight body of a first thickness and having respective ends bounded by integrally formed and oppositely projecting horizontal tabs, said tabs having respective contact engagement surfaces and formed with a dimple disposed on said contact engagement surface.
 4. An elastomeric connector according to claim 3 wherein: said engagement surfaces are formed with chamfered edges.
 5. A compliant interconnect array for maintaining electrical connection between opposing arrays of contacts on a prober interface board and a probecard, respectively, said compliant interconnect ring including: a retainer formed with a plurality of spaced-apart windows; and a plurality of elastomeric connectors, each of said connectors complementally formed to mount within a corresponding window and comprising a thin layer of foam material; and a plurality of formed contact pins embedded in spaced-apart relationship in said foam material, each of said contact pins including a substantially straight body of a first thickness and having respective ends bounded by integrally formed and oppositely projecting horizontal tabs, said tabs having respective contact engagement surfaces and formed with a dimple disposed on said contact engagement surface.
 6. A compliant interconnect array according to claim 5 wherein: said engagement surfaces are formed with chamfered edges. 